The semiconductor devices such as the charge coupled device (CCD) and the CCD solid state imaging device are very useful devices in the field of the semiconductor device. A possibility of realizing such device showing superior properties seems to depend upon the fabrication processes for the semiconductor devices. For that reason, the importance of developments in newly and useful fabrication processes for such devices would be considerable.
In conventional fabrication processes for such the devices, in order to prevent any decrement of the active region, a selective oxidation is accomplished to form a relatively thick silicon oxide film on an active region in the device so that the relatively thick silicon oxide film is used as a mask for ion-implantation to form an isolation region in the active region with use of the self-alignment technique. The above matters are disclosed in the Japanese laid-open patent applications 60-206142 and 2-404974. One of the typical and conventional fabrication method for the solid state imaging device including a charge transfer region, an opto-electro conversion region and an isolation region will be described with reference to FIGS. 1A to 1F.
With reference to FIG. 1A, an n-type semiconductor substrate 501 is prepared to be formed with a p-type well region 502 thereon. A silicon oxide film 503 having a thickness of approximately 40 nanometers is grown on a top surface of the p-type well region 502 and subsequently a silicon nitride film 504 having a thickness of approximately 220 nanometers is grown on a top surface of the silicon oxide film 503. A first photo-resist film is provided on an entire surface of the silicon nitride film 504 to be patterned for a formation of a first photo-resist pattern 520a. The silicon nitride film 504 is selectively removed by a plasma etching in which the first photo-resist pattern 520a is used as a mask.
With reference to FIG. 1B, the first photo-resist pattern 520a is completely removed, after which a second photo-resist pattern is provided on the top surface of the device so as to cover the remaining silicon nitride film 504. The second photo-resist film is patterned to be selectively removed so that a second photo-resist pattern 520b is formed in a predetermined area within which a charge transfer region will be provided. An ion-implantation of an n-type dopant into the p-type well region 502 is accomplished with use of both the second photo-resist pattern 520b and the remaining silicon nitride film 504. The thickness of the silicon oxide film 503 is so very thin as to enable the n-type dopant to penetrate through the silicon oxide film 503 and implanted into a predetermined upper portion of the p-type well region 502. Thus, an n-type region serving as an opto-electro conversion region 506 is selectively formed at the predetermined upper portion of the p-type well region neither covered by the remaining silicon nitride film 504 nor covered by the second photo-resist pattern 520b.
With reference to FIG. 1C, the second photo-resist pattern 520b is removed before a third photo-resist film is provided on the top surface of the device so as to cover the remaining silicon nitride film 504. The third photo-resist film is patterned to be selectively removed so that a third photo-resist pattern 520c is formed to overlay an area except in the opto-electro conversion region 506. An ion-implantation of an n-type dopant into the p-type well region 502 is accomplished with use of both the third photo-resist pattern 520c and the remaining silicon nitride film 504. An n-type region serving as a charge transfer region 507 is selectively formed at an exposed upper portion of the p-type well region 502 which is neither covered with the remaining silicon nitride film 504 nor covered by the third photo-resist pattern 520c.
With reference to FIG. 1D, the third photo-resist pattern 520c is removed. The entire surface of the device is subjected to a selective thermal oxidation wherein the remaining silicon nitride film 504 serves as a mask. Namely, an exposed portion of the silicon oxide film 503, which is not covered with the remaining silicon nitride film 504, is subjected to the selective thermal oxidation so that the exposed portion thereof is grown into a relatively thick silicon oxide film 508 which has a thickness of approximately 300 nanometers. Since the remaining silicon nitride film 504 serving as a mask overlay surface areas of the device except for any active regions, the relatively thick silicon oxide film 508 is provided over the active regions such as the opto-electro conversion region 506 and the charge transfer region 507.
After the selective thermal oxidation of silicon, the remaining silicon nitride film 504 is completely removed by wet etching. An ion-implantation of a p-type dopant such as boron is accomplished with use of the relatively thick silicon oxide film 508 as a mask. The relatively thick silicon oxide film 508 has such sufficient thickness as to serve as a mask while the relatively thin silicon oxide film 503 is so thin as to enable the p-type dopant to penetrate through the relatively thin silicon oxide film 503 and implanted into the upper portion of the p-type well region 502 except in the active regions such as the opto-electro conversion region 506 and the charge transfer region 507. The above ion-implantation of the p-type dopant forms by self-alignment technique a p-type signal read region 510 having a higher dopant concentration than a dopant concentration of the p-type well region 502. A threshold value of the p-type signal read region 510 is controlled by the ion-implantation of the p-type dopant.
A fourth photo-resist film is provided on an entire top surface of the device to cover the relatively thick and thin silicon oxide films 508 and 503. The fourth photo-resist film is patterned to be made into a fourth photo-resist pattern 520d which exists only over the p-type signal read region 510 and its peripheral region. Then, neither part of the relatively thin silicon oxide film 503 nor all part of the relatively thick silicon oxide film 508 is covered by the fourth photo-resist pattern 520d. An additional ion-implantation of a p-type dopant such as boron is accomplished in which both the fourth photo-resist pattern 520d and the relatively thick silicon oxide film 508 serve as masks. The p-type dopant penetrates through the relatively thin silicon oxide film 503 which is not covered by the fourth photo-resist pattern 520d and implanted into the upper portion of the p-type well region 502 except both in the p-type signal read region 510 and in the active regions such as the opto-electro conversion region 506 and the charge transfer region 507. The above additional ion-implantation of the p-type dopant forms by self-alignment technique a p.sup.+ -isolation region 511 having a higher dopant concentration than dopant concentrations of the p-type well region 502 and the p-type signal read region 510. The p.sup.+ -isolation region 511 is provided to isolate the opto-electro conversion region 506 from the charge transfer region 507.
With reference to FIG. 1E, the fourth photo-resist pattern 520d as well as the relatively thin and thick silicon oxide films 503 and 508 are removed before a thermal oxidation is accomplished to form a first gate oxide film which is not illustrated. Subsequently, a first charge transfer electrode which is not illustrated is formed by use of a low pressure chemical vapor deposition method, a photo-lithography method and a plasma etching method. The first charge transfer electrode serves to conduct the charge transfer. The first gate oxide film is selectively removed by an etching in which the first charge transfer electrode is used as a mask, provided that none of the second charge transfer electrode 531 exists over the opto-electro conversion region 506. An additional thermal oxidation is accomplished to form a second gate oxide film 530 on an entire top surface of the device. Subsequently, a second charge transfer electrode 531 is formed by use of the low pressure chemical vapor deposition method, the photo-lithography method and the plasma etching method. The second charge transfer electrode serves to conduct both a read operation of a signal charge and a charge transfer from the opto-electro conversion region 506 to the charge transfer region 507. A further ion-implantation of a p-type dopant such as boron is accomplished with use of the charge transfer electrode 531 as a mask to form a p.sup.+ -type shallow region 512 over the opto-electro conversion region 506. The gate oxide film 530 is so thin as to enable the p-type dopant to penetrate through the second gate oxide film 530 and implanted into an upper portion of the n-type opto-electro conversion region 506. In this further ion-implantation, the p-type dopant is implanted at such an energy that the p-type dopant is limited to the shallow upper portion of the n-type opto-electro conversion region 506. The above further ion-implantation is continued until the shallow upper portion of the n-type opto-electro conversion region 506 is made into the p.sup.+ -type shallow region 512.
With reference to FIG. 1F, an inter-layer insulator 532 is deposited to cover both the charge transfer electrode 531 and an exposed portion of the second gate oxide film 530. A contact hole which is not illustrated is formed in the interlayer insulator so that a part of the charge transfer electrode 531 is exposed through the contact hole. A metal film 533 to serve not only as a wiring but also as a photo mask is selectively formed on part of the inter-layer insulator 532 over the charge transfer electrode 531. A protective silicon oxide film 534 is formed on an entire surface of the device to cover both the metal film 533 and an exposed surface of the inter-layer insulator 532 thereby the conventional fabrication processes for the solid state imaging device are completed.
As described above, in the conventional fabrication method of the solid state imaging device, the relatively thick silicon oxide film is selectively formed by a selective thermal oxidation over the active regions such as the opto-electro conversion region 506 and the charge transfer region 507 so that the relatively thick silicon oxide film is able to serve as a mask for the ion-implantation of the p-type dopant to form by self-alignment technique the p.sup.+ -type isolation region between the opto-electro conversion region 506 and the charge transfer region 507.
Such the conventional fabrication method of the semiconductor device is unavoidably engaged with the following serious problems. The upper portions of the active regions such as the opto-electro conversion region and the charge transfer region are subjected to the selective thermal oxidation. First, this causes a dislocation loop in silicon crystal structure of the upper portion of the active region. The dislocation loop provides an disarrangement of silicon atoms and thus provides an imperfection of crystal or lattice structure of silicon. Second, this further causes both capturing a dopant of the active region into the silicon oxide film and a pile up phenomenon namely accumulating the dopant thereof on a surface of the active region without any capturing into the silicon oxide film. This causes a variation in an impurity concentration profile. The appearance of the dislocation loop and the variation of the impurity concentration profile provide inferiorities in device performances or properties.
In the conventional fabrication method, the p.sup.+ -type isolation region is so formed as to be in contact with the n-type active region. Thus heat treatment for example the thermal oxidation after forming the isolation region causes a lateral diffusion of the p-type impurity in the p.sup.+ -type isolation region. Namely, the p-type impurity is moved into the n-type active regions since the p.sup.+ -type isolation region has a higher impurity concentration than an impurity concentration of the n-type active region. This provides a decrement of the active regions such as the opto-electro conversion region and the charge transfer region thereby resulting in an inferiorities of the device performances or properties.
In the prior arts, the above problems would be unavoidable when the active region has suffered the damage due to any heat treatment such as a selective thermal oxidation of silicon. It would therefore be required to develop a novel and useful fabrication method for the above device free from any of the above problems.